The present invention relates to a synthesizer tuner.
A synthesizer tuner has been widely known as disclosed, for example, in IEEE TRANSACTIONS ON BROADCAST AND TELEVISION RECEIVERS, Vol. BTR-15, No. 3, pp. 235-243, issued in October, 1969. According to the conventional synthesizer tuners, a PLL (phase locked loop) synthesizer is used as a local oscillator to obtain a plurality of local oscillation frequencies separated a predetermined frequency gap. Output signals of a phase comparator in the PLL circuit are applied via a low-pass filter to a varactor diode in a main antenna tuner circuit and to a varactor diode in an interstage tuner circuit between an RF (radio frequency) amplifier and a mixer. Therefore, the difference between a local oscillation frequency and a frequency of received signals can be reduced to a virtually negligible value.
The PLL circuit employed in the coventional synthesizer tuner consists of a programable divider, a reference frequency generator, a phase comparator, a low-pass filter and a voltage controlled oscillator. The voltage controlled oscillator is used as a local oscillator. Upon reception of a predetermined binary signal through a preset terminal, the programable divider produces a frequency-divided signal obtained by dividing the frequency of an output signal of the voltage controlled oscillator by a predetermined dividing ratio. The frequency-divided signal and a reference frequency signal of the reference frequency generator are applied to the phase comparator, and an output signal of the phase comparator is applied via a low-pass filter to the varactor diode in the abovementioned tuner circuit as well as to the voltage controlled oscillator. The output signals of the voltage controlled oscillator that works as a local oscillating circuit are applied to a mixer.
A method of setting the received signal frequencies has also been widely known as disclosed, for example, in Japanese Patent Application Laid-Open Specification No. 52-144211, by providing a channel memory in the synthesizer tuner, storing predetermined binary signals into the channel memory by manipulating a key board, and supplying the stored binary signals into a preset terminal of the programable divider.
In developing a synthesizing tuner in which a plurality of informations for selecting broadcasting stations (i.e., a plurality groups of binary signals) are successively written into a plurality of addresses in the channel memory by operating the key board, to successively read out the plurality of informations for selecting broadcasting stations by successively operating read-out keys of the key board, the inventor of the present invention has found that the same information for selecting broadcasting stations is written two or more times into different addresses, causing the utilization factor of the memory to be decreased. Particularly, when the tuner is used by a plurality of people with the channel memory being composed of a nonvolatile memory, the individual person may individually write information in the memory presenting increased probability of writing information in an overlapped manner.